1. Field of the Invention
The present invention relates to a test apparatus and an electronic device. More particularly, the present invention relates to a test apparatus that tests a device under test and an electronic device including a test circuit that tests a circuit under test.
2. Related Art
A test apparatus for testing a device under test such as a semiconductor has been known. The test apparatus supplies a test signal with a predetermined logical pattern to the device under test, and detects a signal output from the device under test in accordance with this test signal. Then, the test apparatus compares the detected signal and an expected value to decide the good or bad of the device under test.
The test apparatus includes a main memory such as DRAM that stores sequence data (a test instruction stream), a cache memory that temporarily stores a test instruction stream, a transfer section that transfers sequence data from the main memory to the cache memory, a pattern generator that sequentially generates a test pattern, and a test signal output section that outputs a test signal with logic according to the test pattern. The pattern generator sequentially reads instructions from the sequence data stored on the cache memory, and executes the read instructions. Then, the pattern generator reads pattern data corresponding to the executed instructions from the memory, and sequentially outputs the read pattern data as test patterns. According to this, the test apparatus can supply a test signal with a predetermined logical pattern to the device under test.
Moreover, the transfer section sequentially reads sequence data from the main memory, and writes the read data into a space area on the cache memory. When the space area on the cache memory vanishes, the transfer section overwrites the read sequence data on an area on which an executed instruction is stored.
Meanwhile, the test apparatus can include a forward branch instruction in sequence data (for example, see Japanese Patent Application Publication No. 1998-78476). However, since an instruction to be executed next to the forward branch instruction is an already-executed instruction, the instruction may be overwritten by the transfer section. In this case, the pattern generator cannot read an instruction next to the forward branch instruction from the cache memory.
Moreover, in order to generate a test pattern every clock cycle, the pattern generator must perform a series of processes for reading an instruction from the cache memory, executing the read instruction, and then generating an address on the cache memory, in which the address is an address of an instruction to be next executed, for one clock cycle. Furthermore, it is desirable that the pattern generator can generate a test pattern in a shorter clock cycle, and thus it is desirable that a restriction of an executive operation for generating a test pattern is smaller.